To view a particular tutorial click on the appropriate link.
Tutorial1 - VHDL: A Practical Introduction Tutorial 2- Introduction to Modeling with Verilog for Simulation and Synthesis Tutorial 3 - Component Modeling in VHDL/VITAL Tutorial 4 - An Introduction to Rosetta Tutorial 5 - A Tutorial on IP Development in Lava Tutorial 6 - Efficient Coding Style for Maximum VHDL Simulation Performance	Tutorial 7 - Interfacing C-language models to Verilog Simulations Using the Verilog PLI Tutorial 8 - VDSM modeling using ALF Tutorial 9 - SystemC C++ Modeling (part1) The IEEE Standard for VHDL RTL Synthesis: Modeling for portability (part 2) Tutorial 10 - SUAVE: VHDL Extensions for System-Level Modeling Tutorial 11 - Non-Trivial HDL Compilation and Simulation Errors

Tutorial 1 - VHDL: A Practical Introduction Wednesday: 8:30am - 5:30pm Presenter: Paul J. Menchini - Menchini & Associates, USA Description: VHDL: A Practical Introduction is intended to introduce students to VHDL, the IEEE-standard hardware description language. Students will become familiar with all of VHDL's design units, and many of its declarations, specifications, and statements. Students will understand how these elements work together to describe the structure, data flow, and behavior of a digital system.

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Tutorial 2 - Introduction to Modeling with Verilog for Simulation and Synthesis Wednesday: 8:30am - 12:30pm Presenter: Stuart Sutherland - Sutherland HDL, Inc., USA Description: This tutorial is for engineers who wish to understand Verilog. An overview of the language standard will be presented, followed by a look at modeling for simulation and synthesis. Examples will illustrate modeling combinational logic, sequential logic, shift registers, RAMs and tristate logic. A brief discussion of products that support Verilog will also be presented.

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Tutorial 3 - Component Modeling in VHDL/VITAL Wednesday: 8:30am - 12:30pm Presenter: Richard Munden - Acuson Corporation, USA Description: This tutorial will use examples to discuss modeling off-the-shelf components with VHDL and VITAL. Special attention will be given to modeling device path delays and timing constraints. Timing parameters for all models are introduced through SDF backannotation. The tutorial is of interest to anyone using or supporting VHDL for board-level simulation, or learning VITAL for ASIC or FPGA library development.

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Tutorial 4 - An Introduction to Rosetta Wednesday: 8:30am - 12:30pm Presenter: David L. Barton - AverStar, Inc., USA Description: This tutorial will present the basic elements of Rosetta, an emerging systems level design language. Rosetta centers on defining and composing models called facets into systems level descriptions. This tutorial concentrates facet definition, composition and interaction. It is self contained and requires no background in specific languages or design methdologies. Knowledge of VHDL, Verilog or any other hardware description language would be helpful.

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Tutorial 5 - A Tutorial on IP Development in Lava Wednesday: 8:30am - 12:30pm Presenter: Mary Sheeran - Chalmers Tekniska Högskola, Sweden Satnam Singh-Xilinx, Inc., USA Description: This tutorial presents a novel hardware description language called Lava, designed to support highly paramaterised structural circuit descriptions. Although Lava and its tools are still under development, it has been used at Xilinx Inc. to develop IP core generators - highly parameterised circuits which require careful layout for optimum performance or low area utilisation.

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Tutorial 6 - Efficient Coding Style for Maximum VHDL Simulation Performance Wednesday: 8:30am - 12:30pm Presenter: Stephen A. Bailey - Synopsys Inc., USA Description: This tutorial covers RTL coding styles that can significantly decrease RTL verification times for both cycle-optimized simulation and traditional event simulation. The cycle optimization coding styles are based on the Synopsys Inc. Scirocco and Cyclone cyle-optimized VHDL simulators, but should apply to any cycle-optimized VHDL simulator. The event simulation optimization guidelines should apply equally to any event VHDL simulator.

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Tutorial 7 - Interfacing C-language models to Verilog Simulations Using the Verilog PLI Wednesday: 1:30pm - 5:30pm Presenter: Stuart Sutherland - Sutherland HDL ,Inc., USA Description: This tutorial explores use of the Verilog PLI to interface C-language hardware models with Verilog simulators. Synchronous and asynchronous model interfaces are explored, as well as using functions, pipes, and sockets for the interface communication channel. Examples illustrate how to create an interface using any of the PLI libraries (TF, ACC and VPI). The advantages and disadvantages of each interface method are discussed.

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Tutorial 8 - VDSM modeling using ALF Wednesday: 1:30pm - 5:30pm Presenter: Wolfgang Roethig - NEC Electronics, USA Description: This tutorial shows how the Advanced Library Format (ALF) can be efficiently used for a complete description of libraries, cells and blocks in VDSM design. Modeling for function, timing, power, signal integrity of cells and complex blocks in hierarchical design will be explained. Emphasis will be on new features which have been developed since the ALF tutorial at HDLCON in 1998.

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Tutorial 9 consists of two joint sessions. Attendees may register for one session at $100, or may attend both for $200. Each session lasts two hours. Tutorial 9 (part 1) - SystemC C++ Modeling Wednesday: 1:30pm - 3:30pm Presenter: Kurt Schwartz - Williamette HDL, Inc., USA Description: C++ is widely used as a system level modeling language. This tutorial will teach the basics of SystemC C++ modeling infrastructure for system level hardware and software design. Tutorial participants will learn the basic language ideas. The benefits of this system design infrastructure will be explained. Basic knowledge of C and either VHDL or Verilog is useful. Tutorial 9 (part 2) - The IEEE Standard for VHDL RTL Synthesis: Modeling for Portability Wednesday: 3:30apm - 5:30pm Presenters: J. Bhasker - Cadence Design Systems, USA, Douglas J. Smith - Mentor Graphics, USA Description: This tutorial will present the VHDL RTL synthesizable subset standard (IEEE 1076.6). It will give a brief history of the standard followed by a detailed discussion of why specific constructs are supported, not supported, or ignored. The tutorial will then use examples to illustrate features of the standard and highlight portability issues.

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Tutorial 10 - SUAVE: VHDL Extensions for System-Level Modeling Wednesday: 1:30pm - 5:30pm Presenter: Peter J. Ashenden - University of Adelaide, Australia Description: SUAVE extends VHDL with features for object-orientation, genericity, abstract communication, and dynamic process creation. The aim is to allow VHDL to express behavior and structure of a system in the early stages of the design flow. This tutorial will describe SUAVE and show its use for high-level modeling of hardware/software systems. Examples of behavioural test benches written using the extensions will also be discussed.

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Tutorial 11 - Non-Trivial HDL Compilation and Simulation Errors Wednesday: 1:30pm - 5:30pm Presenter: Joseph Pick - Synopsys, Inc., USA Description: This tutorial will present a wide range of tricks and techniques that will improve overall HDL productivity. Non-trivial HDL compilation and simulation errors based on real-world coding scenarios will be explored and innovative solutions to these problems will be provided. If time permits, simulation/synthesis mismatches will also be discussed. Examples will be provided from both the VHDL and Verilog domains.