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Session 1 - System Level Design Session 2 - Mixed Language • Panel 1 - System Level Design Language Strategies a User's Perspective Session 3 - Formal Verification Session 4 - Reuse and IP Delivery • Panel 2 - Migration Between ASICs and FPGAs	Session 5 - Mixed Signal Session 6 - Language Standards Session 7 - Testbenches and Verification • Panel 3 - Verilog 2000 and Beyond Session 8 - Codesign/Coverification Session 9 - Reuse and IP Delivery

Session 1 - System Level Design Thursday: 10:30am - 12:00pm Room: Donner Chair: Greg Peterson - FTL Systems, Inc. 1.1 System Level Design for SOC’s: A Progress Report – Two Years On Grant Martin, Bill Salefski - Cadence Design Systems, Inc., USA 1.2 Fast Software-Level Power Estimation for Design Space Exploration Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto - Politecnico di Milano, Italy 1.3 Superlog, A Next Generation Systems Design Language Peter L. Flake, Simon J. Davidmann, David J. Kelf - Co-Design Automation, Inc., 1.4 The Rosetta Functional Requirements Specification Domains

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Session 2 - Mixed Language Thursday: 10:30am - 12:00pm Room: Monterey Chair: Stuart Sutherland - Sutherland HDL, Inc. 2.1 Integrating Behavioral VHDL and Verilog in ASIC Verification Environments Michael D. McKinney - Texas Instruments, Inc., USA 2.2 A Mixed C/Verilog Dual-Platform Simulator David A. Burgoon, Edward W. Powell, John A. Sundragon Waitz - Hewlett-Packard Co., USA 2.3 Combining VHDL, Verilog and High-Level Languages Under an Advanced Compiler Construction Environment George Economakos, Petros Economakos and Panayiotis Tsanakas - National Technical

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Panel 1 - System-Level Design Language Strategies, a User’s Perspective Friday: 1:30pm - 3:00pm Room: Donner Organizers: William Billowitch, Tedd Corman, David Kelf, Ron Waxman Moderator: Ron Waxman As SoC devices become more prevalent, new methodology constraints are driving an examination of design language options. This panel will provide a designer's perspective of various language proposals, including C++ (Open System C, Cynlib, Spec C), SLDL, Java, Superlog, and VHDL200X, and consider the technical capabilities that they enable, given the trends in modern design and current methodologies. Panelists: George Plouffe - Sun Microsystems, Inc. Oz Levia - Improv Systems, Inc. Steve Schulz - Texas Instruments Tadatoshi Ishii - Toshiba Corp. Anders Nordstrom - Nortel Networks William Billowitch - Intrinsix Corp. Paul Menchini - Cadence Design Systems, Inc.

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Session 3 - Formal Verification Thursday: 3:30pm - 5:00pm Room: Monterey Chair: Jayaram Bhasker - Cadence Design Systems, Inc. 3.1 Symbolic Simulation and Verification of VHDL with ACL2 Dominique Borrione, Philippe Georgelin, Vanderlei Moraes Rodrigues - TIMA Lab., France 3.2 Expanding Formal Verification in a Systems Environment

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Session 4 - Reuse and IP Delivery Thursday: 3:30pm - 5:00pm Room: Donner Chair: Cliff Cummings - Sunburst Design, Inc. 4.1 A Methodology for Automating Design Reuse Allen Wu - Y Explorations, Inc., USA John Hillawi - DA Solutions, Ltd., UK Bill McNamara - Y Explorations, Inc., USA 4.2 A Case Study: Design Reuse and Intellectual Property to Meet an Accelerated Design Schedule Ronald Crevier, Larry Specter - Mentor Graphics Corp., USA 4.3 Constraint-Based Specification of Complex Components Cristina Buchholz, Wolfgang Rosenstiel - FZI, Karlsruhe, Germany 4.4 Intermediate Format Standardization: Ambiguities, Deficiencies, Portability Issues, Documentation and Improvements Amir Masoud Gharehbaghi, Mohammad Hossein Reshadi - University of Tehran, Iran

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Panel 2 - Migrating Between ASICs and FPGAs Challenges and Solutions for HDL Based High Density, SoC Designs Using IP Cores in FPGA Versus ASIC Environment. Friday: 8:30am - 10:00am Room: Donner Organizer: L. Eric Culverson Moderator: L. Eric Culverson High density FPGAs replace ASICs in end-systems while ASICs replace FPGAs in high volume production. The panel will discuss: - ASIC design flow versus FPGA - challenges of SoC in an FPGA device - timing verification strategies - IP re-use of across FPGA & ASIC and devices Panelists: Preeth Chengapba- Synplicity R&D L. Eric Culverson - TSI Jeffery Fox - Altera R & D Bill Johnston - Avnet Design Services Hitesh Patel - Xilinx R & D

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Session 5 - Mixed Signal Friday: 8:30am - 10:00am Room: Monterey Chair: Tom Kazmierski - Univ. of Southampton 5.1 Reasons Why Digital Designers Should Care About VHDL-AMS Greg Peterson, John Willis - FTL Systems, Inc., USA 5.2 Elaboration of Hierarchical VHDL-AMS Models for Mixed-Signal Simulation Jochen Mades - Infineon Technologies and Technical University of Darmstadt, Germany Thomas Schneider - Technical University of Darmstadt, Germany Andre Windisch - Technical University of Chemnitz, Germany Wolfgang Ecker - Infineon Technologies, Germany 5.3 Dimensions in Design Languages

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Session 6 - Language Standards Friday: 10:30am - 12:00pm Room: Donner Chair: John Hillawi - DA Solutions Ltd. 6.1 VHDL in 2005 - The Requirements Robert H. Klenke - Virginia Commonwealth University, USA James H. Aylor - University of Virginia, USA Paul Menchini - Cadence Design Systems, Inc., USA Ronald Waxman - EDA Standards Consulting, USA William Anderson, Jack Stinson - Advanced Technology Institute, USA 6.2 The IEEE Verilog 1364-2000 Standard: What's New, and Why You Need It Stuart Sutherland - Sutherland HDL Inc., USA 6.3 A Proposal To Remove Those Ugly Register Data Types From Verilog Cliff Cummings - Sunburst Design, Inc., USA 6.4 Automating the Validation of Hardware Description Language Processing Tools Greg Peterson - FTL Systems, Inc., USA Sathyanarayanan Seshadri, Sanjeev Thiyagarajan - University of Cincinnati, USA John Willis - FTL Systems, Inc., USA

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Session 7 - Testbenches and Verification Friday: 10:30am - 12:00pm Room: Monterey Chair: Chris Spear - Synopsys, Inc. 7.1 TCL_PLI, a Framework for Reusable, Run Time Configurable Test Benches Stephan Voges, Mark Andrews - Electronics For Imaging, Inc., USA 7.2 A Functional Verification Methodology Using Code Coverage John Colley - TransEDA, USA 7.3 Powerful Frontend of a Synchronization Unit for a Pure VHDL-Based Testbench Environment Matthias Bauer, Wolfgang Ecker, Andreas Zinn - Infineon Technologies, Germany 7.4 Functional Verification with Embedded Checkers Scott Switzer - SmartSand, Inc., USA

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Panel 3 - Verilog-2000 and Beyond Friday: 1:30pm - 3:00pm Room: Donner Organizer: Cliff Cummings Moderator: Cliff Cummings At the 1996 International Verilog Conference, a panel was organized to discuss proposals for the "top five" enhancement requests for the Verilog language. Every "top five" enhancement request has been incorporated into the proposed IEEE 1364 Verilog-2000 standard and will be discussed during panelist presentations.. Panelists: Cliff Cummings - Sunburst Design, Inc. Anders Nordstrom - Nortel Networks, Inc. Karen L. Pieper - Synopsys, Inc. Michael McNamara - Verisity Design Kurt Baty - WSFDB Consulting TBD - SystemC

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Session 8 - Codesign/Coverification Friday: 3:30pm - 5:00pm Room: Donner Chair: Gabe Moretti 8.1 Virtual Component HW/SW Co-Design - From System Level Design Exploration to HW/SW Implementation Frank Schirrmeister, Stan Krolikoski - Cadence Design Systems, Inc., USA 8.2 Hardware/Software Co-Verification of CDMA ASIC Designs Siddhartha Ray Chaudhuri - Qualcomm, USA Russell Klein - Mentor Graphics Corp., USA 8.3 Automated Design Space Exploration on System Level for Embedded Systems

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Session 9 - Reuse and IP Delivery Friday: 3:30pm - 5:00pm Room: Monterey Chair: Dennis Brophy - Model Technology 9.1 RTL Handoff - Solving the Time To Market Issue? Anders Nordstrom - Nortel Networks Inc., Canada 9.2 Life in the Fast Lane: Synthesis Above the Register-Transfer Level David W. Knapp - Get2Chip.com, USA 9.3 High Level Modeling and Synthesis of Digital Filters J. R. Armstrong - Virginia Tech, USA 9.4 Performance Tradeoffs for Emulation, Hardware Acceleration, and Simulation