8:30 - 10:00	Panel 2 - Migration Between ASICs & FPGAs Session 5 - Mixed Signal
10:00 - 10:30	break
10:30 - 12:00	Session 6 - Language Standards Session 7 - Testbenches and Verification
12:00 - 1:30	lunch (in exhibit area)
1:30 - 3:00	Panel 3 Verilog 2000 and Beyond
3:00 - 3:30	break
3:30 - 5:00	Session 8 - Codesign/Coverification Session 9 - Miscellaneous