The Call for Papers is now available. Submission deadline is Wednesday, December 15. Suggested topics, meant to address system-level design issues, include, but are not limited to: hardware/software co-design; behavioral coding and synthesis; VHDL/Verilog HDL co-simulation and advanced techniques; formal verification; architectural design trade-offs; emulation and virtual prototyping; and intellectual property (IP) capture, protection and distribution. Submit your paper or abstract today!

The conference attracts electronic designers, verification engineers and design managers, and members of the electronic design automation (EDA) community. It has become the premier forum to learn about innovative HDL design techniques that solve next-generation and system on chip (SOC) design challenges.

The exhibition features EDA vendors showing the latest tools for the development of consumer electronics, telecommunications and computers. You will find the design tools to improve your knowledge of the use of HDLs in your design flow.

This conference is sponsored by Open Verilog International (OVI), VHDL International (VI), and VHDL International User Forum (VIUF). In cooperation with IEE Professional Group A2 (Hardware Systems Engineering) and ECSI.

• About the Conference
• Registration Information
• Technical Program
• Exhibit Information
• Press Information

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